Job Details

Efficient is developing the world's most energy-efficient general-purpose computer processor. Efficient's patented technology uses 100x less energy than state of the art commercially available ultra-low-power processors and is programmable using standard high-level programming languages and AI/MLframeworks. This level of efficiency makes perpetual, pervasive intelligence possible: run AI/ML continuously on a AA battery for 5-10 years. Our platform's unprecedented level of efficiency enables IoT devices to intelligently capture and curate first-party data to drive the next major computing revolution

Efficient's Lead Physical Design Engineer will design and implement our chip through tape-out. If you are an engineer who wants to be part of an intensely skilled team and wants to have an immediate impact on the design and implementation of our chip, this is for you! We seek individuals to leverage low-power techniques and design-technology co-optimization in advanced technology nodes to build energy-efficient SoCs.

This is a unique opportunity to get in at the ground level and have influence on our products as we move from initial stages of product development to market release and scaled volume production. Join our team and help us shape the future of computing at the edge and beyond!

Key Responsibilities

• Lead physical design team from synthesis to sign-off and tape-out
• Run physical design tasks including synthesis and place-and-route
• Work with digital design team to integrate analog and digital IP into design
• Interact with design verification team and run verification tasks on design
• Resolve DRC & LVS violations to produce DRC-clean GDS-II of chip to deliver to foundry
• Interact with foundry partners through multi-party wafer and manufacturing runs
• Interact with backend services partners on physical design tasks through sign-off
• Implement and execute physical design management process with PD team
• Setup and maintain physical design tools, primarily Synopsys, but also potentially including Mentor/Siemens EDA, Cadence, or ANSYS tools as necessary
• Run power and energy modeling on synthesized, place-and-routed design
• Interact with digital design team to resolve RTL-level issues leading to DRC violations
• Mentor and train junior hardware physical design engineers

Required Qualifications & Experience Requirements

• Must be an outstanding leader in physical design with substantial experience successfully bringing real chips from design to tape-out.
• Master's degree in Electrical Engineering with 7+ years of industry experience or PhD in Electrical Engineering with 5+ years of industry experience.
• Experience running physical design tasks using Synopsys and/or Cadence EDA tools.
• Experience interacting with chip foundry services companies.
• Experience integrating analog and digital IP into prior tape-outs
• Experience with post-silicon bring-up and working with post-silicon validation team
• Experience with performing verification and interacting with verification and design teams
• Experience with power and energy modeling
• Experience with continuous integration and testing
• Strong attention to detail, good work ethic, ability to work on multiple projects simultaneously, and good communication skills

We offer a competitive salary for this role, generally ranging from $200,000 to $230,000, along with meaningful equity and comprehensive benefits. The final compensation package will be based on your experience and location, with some flexibility to ensure we align with the right candidate.

Why Join Efficient?

Efficient offers a competitive compensation and benefits package, including 401K match, company-paid benefits, equity program, paid parental leave, and flexibility. We are committed to personal and professional development and strive to grow together as people and as a company.